The present invention concerns phase locked loop (PLL) synchronization systems and in particular, a PLL system in a video signal resampling system which generates a synchronized clock signal for a phase alternate line (PAL) output video signal using phase information from the input video signal.
Sample rate conversion systems are well known for converting television and other video signals from one format to another. An exemplary video signal standards conversion system is described in U.S. Pat. No. 5,057,911 entitled, SYSTEM AND METHOD FOR CONVERSION OF DIGITAL VIDEO SIGNALS, which is hereby incorporated by reference for its teachings on digital resampling techniques.
The system described in the above-referenced patent converts a component video signal having a nominal sample rate of 13.5 MHz into a digital signal having a sample rate of 14.31818 MHz, (hereinafter 14.3 MHz) which is compatible with the National Television Standards Committee (NTSC) Standard. The ratio of these two sample frequencies is exactly equal to the ratio of 33 to 35.
To obtain good performance from the resampling system it is desirable for the output sample clock signal to be locked in phase with the input sample clock signal. In the referenced patent, this may be achieved relatively easily by dividing the input sample clock signal by 33 and dividing the output sample clock signal by 35, applying both divided signals to a phase comparator and using the output signal of the phase comparator (not shown) to adjust the phase of the output clock signal.
These simple techniques are ineffective, however, for synchronizing an output clock signal for a phase alternate line (PAL) video signal to a standard studio component video signal, such as a CCIR 601 (625/25) signal. This signal has the same line and frame format as a PAL television signal (i.e. 625 lines/frame and 25 frames per second) but it uses a sample clock signal of 13.5 MHz which is 864 times the frequency of the horizontal line synchronization component of the video signal. The ideal sample clock signal for a sampled data PAL television signal, on the other hand, is 17.734475 MHz (hereinafter 17.7 MHz) four times the color subcarrier frequency (4*f.sub.sc). This color subcarrier frequency, f.sub.sc, is related to the horizontal line frequency (f.sub.h) according to the equation (1). EQU f.sub.sc =1135*f.sub.h /4+25 (1)
Because of the 25 Hz offset which is added to the color subcarrier frequency, the largest common frequency between the 13.5 MHz input clock signal and the 17.7 MHz output clock signal is 50 Hz. If the output clock signal were synchronized to the input clock signal at this low frequency, the jitter in the resulting output clock signal would be so great as to make it unusable.
In this sense, the input and output clock signals are incompatible; neither signal can be directly locked in frequency and phase to the other signal using conventional phase locking techniques.
In existing conversion systems, an analog reference video signal, such as
color bars or black burst is used to gen-lock both the digital component input signal and the digital composite output signal. The digital component input signal uses the horizontal pulses of the reference signal as its phase reference while the digital composite output signal uses the color burst of the reference signal as its phase reference. The frame information (i.e. which frame of the multi-frame sequence is currently being processed) is used as a coarse adjustment for both the input and output signals. This method requires get-lock capability in the component source and an external reference signal.